Static verification tools, available in EDA systems, are used by circuit designers to be in compliance with design specifications of various aspects of circuit designs, such as low power, asynchronous clocks, functionality, style, and structure, for example.
Typical designs may vary in complexity. For example, the number of digital logic gates may range from dozens to billions. Similarly, auxiliary data associated with power formats and clocks that may be required for static verification may also be very complex.
Static verification tools typically take a design and any auxiliary data as input, perform complex analysis, and produce reports containing many separate messages, including information about potential violations of conformance with design specifications. Each message or violation may indicate some problem in the design or auxiliary data, or in their interaction, and may have one or more fields containing at least one pointer to a part of the design, a part of auxiliary data, or both.
A typical verification tool report may contain thousands or millions of messages or violations. To progress toward a solution, a designer may typically analyze the report manually, sort or group the reported messages or violations, and make guesses or inferences to try to deduce at least one root cause of the violations. Typically, manual analysis may be aided by techniques such as visual display of the design and/or any auxiliary data, tracing of the design, knowledge of the design and any auxiliary data, knowledge of the domain, using additional commands provided by the static verification tools, or any combination of the above techniques. Typically, domain knowledge refers to the experience gathered in an area of work, such as static verification of compliance with low-power specifications, linting, or clock-domain crossing (CDC), to name a few examples. This manual process may be slow and error-prone. For example, unrelated violations may be grouped together, which may cause added difficulty in identifying root causes or determining which violations are root-cause violations.
Root-cause analysis may play a large role in facilitating solutions of problems in circuit designs that result in violations at the verification stage. For at least the reasons described above, conventional static verification tools tend to be inefficient, slow, and costly with respect to root-cause analysis, adding to the overall cost of circuit design and verification.